Semiconductor device and method for manufacturing the same

ABSTRACT

A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present appliction This is an application for reissue of U.S. Pat.No. 8,692,352 issued on Apr. 8, 2014, and is continuation of applicationSer. No. 15/093,108 filed on Apr. 7, 2016, which is also an applicationfor reissue of U.S. Pat. No. 8,692,352, from U.S. patent applicationSer. No. 13/725,389 filed on Dec. 21, 2012, which is a Continuation ofU.S. application Ser. No. 12/882,863 filed on Sep. 15, 2010, now U.S.Pat. No. 8,357,989, which in turn claims priority from Japaneseapplication No. 2009-213345 filed on Sep. 15, 2009, the entire contentsof each of which are hereby incorporated by reference into thisapplication.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method formanufacturing the same and more particularly to a semiconductor devicehaving a trench and a method for manufacturing the same.

A device isolation (deep trench isolation, or DTI) structure in whichinsulating film is filled in a trench with a high aspect ratio isdisclosed in Japanese Unexamined Patent Publication No. 2002-118256.

In the technique described therein, a trench is first made in a surfaceof a semiconductor substrate and then a first insulating film is formedover the surface of the semiconductor substrate in a manner to fill thetrench. An opening which reaches the first insulating film is made byanisotropic etching of the first insulating film, where the upper endcorner of the opening of the first insulating film has a more gradualinclination than the upper end corner of the trench. The aboveanisotropic etching process also reduces the thickness of the firstinsulating film lying over the semiconductor substrate surface. Afterthat, a second insulating film is formed over the semiconductorsubstrate surface in a manner to fill the opening.

After a DTI structure was formed as mentioned above, an electronicdevice such as a MOSFET (metal oxide semiconductor field effecttransistor) is formed on the semiconductor substrate.

SUMMARY OF THE INVENTION

In the above technique, it is necessary to fill the high aspect-ratiotrench with the first and second insulating films. This means that aninsulating film deposition process must be performed twice and ananisotropic etching process to expand the upper end of the opening mustalso be performed, resulting in a longer flow time and an increase inprocessing time and cost.

In addition, if there is an air-gap space in the trench, the air-gapspace may become exposed on the substrate surface by a subsequent wetprocess. If the air-gap space in the trench is exposed on the substratesurface, photo-resist may get into the air-gap space through its exposedportion and become unremovable. The photo-resist in the air-gap spacemay spout and appear as a foreign substance in a later process, causinga pattern defect.

The present invention has been made in view of the above problem and hasan object to provide a semiconductor device which eliminates the needfor high fillability through a simple process and a method formanufacturing the same.

According to one aspect of the present invention, a method formanufacturing a semiconductor device includes the following steps.First, a device having a conductive portion is completed on the mainsurface of a semiconductor substrate. Then, a first trench whichsurrounds the device when seen in a plan view is made in the mainsurface of the semiconductor substrate. An insulating film is formedover the device and in the first trench so as to cover the device andmake an air-gap space in the first trench. Then, a hole which reachesthe conductive portion of the device is made in the insulating film.

According to this aspect of the invention, the first trench is madeafter completion of the device, so there is no possibility thatphoto-resist may get into the first trench in the course of making thedevice. Therefore, a semiconductor device which eliminates the need forhigh fillability through a simple process and a method for manufacturingthe same can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view showing the structure of a semiconductordevice according to a first embodiment of the present invention in theform of a chip;

FIG. 2 is a partially sectional perspective view showing a deviceformation region shown in FIG. 1 as surrounded by a trench when viewedin a plan view;

FIG. 3 is a schematic sectional view showing the structure of thesemiconductor device according to the first embodiment as a devicesurrounded by the trench as shown in FIG. 2;

FIG. 4 is a schematic sectional view showing a first step in the methodfor manufacturing the semiconductor device according to the firstembodiment;

FIG. 5 is a schematic sectional view showing a second step in the methodfor manufacturing the semiconductor device according to the firstembodiment;

FIG. 6 is a schematic sectional view showing a third step in the methodfor manufacturing the semiconductor device according to the firstembodiment;

FIG. 7 is a schematic sectional view showing a fourth step in the methodfor manufacturing the semiconductor device according to the firstembodiment;

FIG. 8 is a schematic sectional view showing a fifth step in the methodfor manufacturing the semiconductor device according to the firstembodiment;

FIG. 9 is a schematic sectional view showing a sixth step in the methodfor manufacturing the semiconductor device according to the firstembodiment;

FIG. 10 is a schematic sectional view showing a seventh step in themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 11 is a schematic sectional view showing an eighth step in themethod for manufacturing the semiconductor device according to the firstembodiment;

FIG. 12 is a schematic sectional view showing a ninth step in the methodfor manufacturing the semiconductor device according to the firstembodiment;

FIG. 13 is a schematic sectional view showing the structure of a sampleused in a device evaluation test for comparison between an air-gap DTIstructure and a solid DTI structure;

FIG. 14 shows the result of a test in which, with voltage applied to oneterminal of the sample shown in FIG, 13, the current flowing in theother terminal was measured;

FIG. 15 shows the result of a test in which the breakdown voltage wasmeasured when the width of the DTI structure of the sample shown in FIG.13 was changed;

FIG. 16A shows the field intensity distribution at breakdown when thereis no air-gap space in the trench of the DTI structure in the sampleshown in FIG. 13 and FIG. 16B is a partially enlarged view thereof;

FIG. 17A shows the field intensity distribution at breakdown when thereis an air-gap space in the trench of the DTI structure in the sampleshown in FIG. 13 and FIG. 17B is a partially enlarged view thereof;

FIG. 18 is a schematic sectional view showing a first step in the methodfor manufacturing the semiconductor device according to a secondembodiment of the invention;

FIG. 19 is a schematic sectional view showing a second step in themethod for manufacturing the semiconductor device according to thesecond embodiment;

FIG. 20 is a schematic sectional view showing a third step in the methodfor manufacturing the semiconductor device according to the secondembodiment;

FIG. 21 is a schematic sectional view showing the method formanufacturing a semiconductor device according to a third embodiment ofthe invention;

FIG. 22 is a schematic sectional view showing a first step in the methodfor manufacturing the semiconductor device according to a fourthembodiment of the invention;

FIG. 23 is a schematic sectional view showing a second step in themethod for manufacturing the semiconductor device according to thefourth embodiment;

FIG. 24 is a schematic sectional view showing a third step in the methodfor manufacturing the semiconductor device according to the fourthembodiment;

FIG. 25 is a schematic sectional view showing a first step in the methodfor manufacturing the semiconductor device according to a fifthembodiment of the invention;

FIG. 26 is a schematic sectional view showing a second step in themethod for manufacturing the semiconductor device according to the fifthembodiment;

FIG. 27 is a schematic sectional view showing a third step in the methodfor manufacturing the semiconductor device according to the fifthembodiment;

FIG. 28 is a schematic sectional view showing an example of isolation byDTI;

FIG. 29 is a schematic sectional view showing another example ofisolation by DTI; and

FIG. 30 is a partially sectional perspective view showing a furtherexample of isolation by DTI.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Next, the preferred embodiments of the present invention will bedescribed referring to the accompanying drawings.

First Embodiment

Referring to FIG. 1, a BiC-DMOS (bipolar complementary double-diffusedmetal oxide semiconductor) chip CH has a logic section LG, for example,as an integration of low breakdown voltage CMOS (complementary MOS)transistors, and output drivers HV which use high breakdown voltagedevices. The region in which the logic section LG is formed issurrounded by a DTI structure when seen in a plan view. In the outputdrivers HV, each device formation region is surrounded by a DTIstructure when seen in a plan view.

Referring to FIG. 2, in the output drivers HV, the device formationregion DFR for each high breakdown voltage device is surrounded by atrench DTR configuring a DTI structure when seen in a plan view. Thistrench DTR is formed in a surface of a semiconductor substrate SUB.

Next, a case that a high breakdown voltage lateral MOS transistor isused as the high breakdown voltage device will be explained.

Referring to FIG. 3, the semiconductor substrate SUB is, for example,made of silicon and selectively has a trench STR in its main surface. Aburied insulating layer BIL is formed in this trench STR. This trenchSTR and buried insulating layer BIL make up an STI (shallow trenchisolation) structure.

A p⁻ epitaxial region EP1 and an n-type buried region NBR are formedover a p-type region PR of the semiconductor substrate SUB. A p-typeburied region PBR is selectively formed over the n-type buried regionNBR. A p⁻ epitaxial region EP2 is formed over the n-type buried regionNBR and p-type buried region PBR.

A high breakdown voltage lateral MOS transistor is formed on the surfaceof the semiconductor substrate SUB in the p⁻ epitaxial region EP2. Thishigh breakdown voltage lateral MOS transistor mainly has an n-typeoffset region NOR, an n-type well region NWR, a p-type well region PWR,an n⁺ drain region DR, an n⁺ source region SO, a gate insulating film GIand a gate electrode layer GE.

The n-type offset region NOR is formed on the surface of thesemiconductor substrate SUB in a manner to make up a pn junction incombination with the p⁻ epitaxial region EP2. The n-type well region NWRis formed in a manner to contact the n-type offset region NOR and the n⁺drain region DR is formed on the surface of the semiconductor substrateSUB in a manner to contact the n-type well region NWR.

The p-type well region PWR is formed on the surface of the semiconductorsubstrate SUB in the p⁻ epitaxial region EP2. The n⁺ source region SO isformed on the surface of the semiconductor substrate SUB in a manner tomake up a pn junction in combination with the p-type well region PWR.The p-type well region PWR and p⁻ epitaxial region EP2 lie between then⁺ source region SO and n-type offset region NOR along the surface ofthe semiconductor substrate SUB.

The gate electrode layer GE is funned over the semiconductor substrateSUB in a manner to face, through the gate insulating film GI, the p-typewell region PWR and p⁻ epitaxial region EP2 lying between the n⁺ sourceregion SO and n-type offset region NOR. One end of the gate electrodelayer GE lies over the STI structure formed in the n-type offset regionNOR. A side wall insulating film SW is formed in a manner to cover theside wall of the gate electrode layer GE.

In this embodiment, it is preferable that a silicide layer SC be formedover the surfaces of the n⁺ source region SO, n⁺ drain region DR andgate electrode layer GE, although this silicide layer SC is omissible.

In the p⁻ epitaxial region EP2, a p-type sinker region PDR is formed ina manner to contact the p-type buried region PBR, where a p-type wellregion PWR and a p+ contact region PCR are formed near the surface ofthe semiconductor substrate SUB in the p-type sinker region PDR. Forelectric isolation between the p+ contact region PCR and n⁺ sourceregion SO, an STI structure is formed in the surface of thesemiconductor substrate SUB between the p+ contact region PCR and n⁺source region SO.

In the p⁻ epitaxial region EP2, an n-type sinker region NDR is formed ina manner to contact the n-type buried region NBR, where an n-type wellregion NWR and a n⁺ contact region NCR are formed near the surface ofthe semiconductor substrate SUB in the n-type sinker region NDR. It ispreferable that a silicide layer SC be formed over the surfaces of then⁺ contact region NCR and p+ contact region PCR, although such asilicide layer SC is omissible.

An insulating film IL1, an insulating film IL2 and an interlayerinsulating film II are stacked in order, covering the high breakdownvoltage lateral MOS transistor. For example, the insulating film IL1 isa silicon oxide film and the insulating film IL2 is a silicon nitridefilm. The interlayer insulating film II is, for example, a laminatecomprised of BP-TEOS (boro-phospho-tetra-ethyl-ortho-silicate) and asilicon oxide film formed over it by plasma CVD (chemical vapordeposition). The BP-TEOS (BPSG: boro-phosphate silicate glass) in theinterlayer insulating film II should include an impure substance whichis at least either a Group-III element or a Group-V element such asP-TEOS (PSG: phosphorus silicon glass) and B-TEOS (BSG: born silicateglass).

A contact hole CH is made in the insulating film IL1, insulating filmIL2 and interlayer insulating film II and a plug conductive layer PL isformed in the contact hole CH. An interconnect layer ICL is formed overthe interlayer insulating film II. The interconnect layer ICL iselectrically coupled through the plug conductive layer PL in the contacthole CH with the conductive portion of the high breakdown voltagelateral MOS transistor MOS (source region SO, drain region DR, contactregions NCR and PCR, gate electrode layer GE and so on).

A DTI structure is formed in a manner to surround the formation regionfor the high breakdown voltage lateral MOS transistor when seen in aplan view. This DTI structure includes a trench (first trench) DTRextending inward from the surface of the semiconductor substrate SUB,and an insulating film II formed in the trench DTR. The trench DTR isformed so as to penetrate the p⁻ epitaxial region EP2, n-type buriedregion NBR and p⁻ epitaxial region EP1 from the surface of thesemiconductor substrate SUB and reach the p-type region PR.

The insulating film II formed in the trench DTR is part of theinterlayer insulating film II formed over the high breakdown voltagelateral MOS transistor. The trench DTR is not completely filled with theinsulating film II but there is an air-gap space SP inside the trenchDTR.

It is preferable that this air-gap space SP be formed at least in thevicinity of the junction between the n-type buried region NBR and p⁻epitaxial region EP1. The height of the air-gap space SP may be almostequal to the depth of the trench. It is preferable that the aspect ratio(depth/width W) of the trench DTR be 1 or higher. It is also preferablethat the width W of the trench DTR be 0.3 μm or more on the premise thatthe breakdown voltage is 80 V.

It is also possible that the trench DTR is formed in a region wherethere is an STI structure. In this case, in a region where the trenchSTR of the STI structure (second trench) is formed, the trench DTRshould be deeper than the trench STR.

Next, a method for manufacturing a semiconductor device which includes ap-channel MOS transistor (hereinafter called a pMOS transistor), a CMOStransistor, and a nonvolatile semiconductor memory as well as a highbreakdown voltage lateral MOS transistor according to this embodimentwill be described referring to FIGS. 4 to 12.

Referring to FIG. 4, first of all, various devices (high breakdownvoltage lateral MOS transistor, pMOS transistor, CMOS transistor, andnonvolatile semiconductor memory) are completed on the surface of thesemiconductor substrate SUB.

The high breakdown voltage lateral MOS transistor includes an n-typeoffset region NOR, an n-type well region NWR, a p-type well region PWR,an n⁺ drain region DR, an n⁺ source region SO, a gate insulating filmGI, and a gate electrode layer GE.

The pMOS transistor as a high breakdown voltage device includes a p-typeoffset region POR, an n-type well region NWR, a p-type well region PWR,a p+ drain region DR, a p+ source region SO, a gate insulating film GI,and a gate electrode layer GE.

The CMOS transistor is formed so as to complete the pMOS transistor andnMOS transistor. The pMOS transistor includes an n-type well region NWR,a pair of LDL (lightly doped drain) p-type source/drain regions S/D,agate insulating film GI, and a gate electrode layer GE. The nMOStransistor includes a p-type well region PWR, a pair of LDL n-typesource/drain regions S/D, a gate insulating film GI, and a gateelectrode layer GE.

The nonvolatile semiconductor memory uses, for example, a stack gatetype memory transistor. The stack gate type memory transistor includes ap-type well region PWR, an LDD n-type drain region DR, an n− sourceregion SO, a gate insulating film GI, a floating gate electrode layerFG, an inter-gate insulating film GBI, and a control gate electrodelayer CG.

A silicide layer SC may be formed on the surfaces of impurity regionssuch as the source regions and drain regions of these devices and on thesurfaces of the gate electrodes. Also, side wall insulating layers SWare formed so as to cover the side walls of the gate electrode layersGE, FG and CG of the devices.

Referring to FIG. 5, an insulating film IL1, an insulating film IL2 anda mask film MK are stacked in a manner to cover the device. Theinsulating film IL1 may be a non-doped silicon oxide film with athickness of 20 nm. The insulating film IL2 may be a silicon nitridefilm with a thickness of 50 nm. The mask film MK may be a non-dopedsilicon oxide film with a thickness of 700 nm. Photo-resist PRE iscoated on the mask film MK.

Referring to FIG. 6, patterning with photo-resist PRE is done by anordinary photoengraving technique. Using the resist pattern PRE made bythis patterning process as a mask, anisotropic etching is performed onthe mask film MK, insulating film IL2, insulating film IL1, and STIstructure in order. Consequently, a trench DTRA is formed in the surfaceof the semiconductor substrate SUB.

Referring to FIG. 7, anisotropic etching is then performed on thesemiconductor substrate SUB using the mask film MK as a mask.Consequently, a trench DTR is formed in a manner to penetrate the p⁻epitaxial region EP2, n-type buried region NBR and p⁻ epitaxial regionEP1 from the surface of the semiconductor substrate SUB and reach thep-type region PR. After that, the mask film MK is removed by isotropicetching.

Referring to FIG. 8, as a result of the above isotropic etching process,the upper surface of the insulating film IL2 is exposed and the buriedinsulating film BIL of the STI structure which is exposed on the wallsurface of the trench DTR is depleted (retracted) laterally as seen inthe figure.

Referring to FIG. 9, an insulating film IIA is formed over each deviceand in the trench DTR in a manner to cover the device and form anair-gap space SP inside the trench DTR. This insulating film 11A may bea BP-TEOS film with a thickness of 1450 nm. The upper surface of theinsulating film 11A is flattened, for example, by CMP (chemicalmechanical polishing). As a consequence, the thickness of the insulatingfilm 11A becomes, for example, 750 nm.

Referring to FIG. 10, a silicon oxide film is formed over the insulatingfilm IIA by a plasma CVD process. The insulating film IIA and thesilicon oxide film thus formed by the plasma CVD process make up aninterlayer insulating film II.

Referring to FIG. 11, a contact hole CH is made by an ordinaryphotoengraving technique and an etching technique in a manner topenetrate the interlayer insulating film II, insulating film IL2 andinsulating film IL1 and reach the surface of the semiconductor substrateSUB. For example, the surface of the silicide layer SC formed on thesurfaces of the source and drain regions is exposed through this contacthole CH.

Referring to FIG. 12, a plug conductive layer PL is formed in thecontact hole CH. After that, an interconnect layer ICL is formed overthe interlayer insulating film II for electric coupling with theconductive portion of the device through the plug conductive layer PL.

The semiconductor device according to this embodiment is manufactured bythe above procedure. Next, an explanation will be given of the result ofthe inventors' tests to investigate differences in characteristics (leakcurrent, breakdown voltage, field intensity distribution at breakdown)between a DTI structure with an air-gap space in a trench DTR (air-gapstructure) and one without such a space (solid structure).

First, samples which were used in the above tests to investigate thecharacteristics are explained below referring to FIG. 13. In the sampleas shown in FIG. 13, a p⁻ epitaxial region EP1, an n-type buried regionNBR, and a p⁻ epitaxial region EP2 are stacked over a p-type region PRof a semiconductor substrate SUB. A trench DTR is formed in thesemiconductor substrate SUB in a manner to penetrate the p⁻ epitaxialregion EP1, n-type buried region NBR, and p⁻ epitaxial region EP2 fromits surface and reach the p-type region PR. An insulating film II isformed in this trench DTR. One side of the p⁻ epitaxial region EP2 withrespect to the trench DTR is electrically coupled with a conductivelayer CL1 and the other side is electrically coupled with a conductivelayer CL2.

The inventors measured leak currents flowing between the conductivelayers CL1 and CL2 when the voltage VH applied to the conductive layerCL1 was changed under the following different sample conditions: thewidth of the trench DTR (DTI width) W was 0.6 μm, 0.8 μm and 1.0 μm.FIG. 14 shows the result of the test.

Referring to FIG. 14, whereas the leak current was found to be between1×10⁻¹⁰ A and 1×10⁻⁹ A regardless of the width W of the trench DTR whenthe trench DTR had no air-gap space SP, the leak current was found to beless than 1×10⁻¹⁰ A when the trench DTR had an air-gap space SP. Thisdemonstrates that the leak current is lower when the trench DTR has anair-gap space SP than when it has no air-gap space SP.

The inventors conducted a test to find how the breakdown voltage changesaccording to the width W of the trench DTR (DTI width). FIG. 15 showsthe result of the test.

Referring to FIG. 15, when the trench DTR had no air-gap space SP, thebreakdown voltage BV rose as the width W of the trench DTR was changedfrom 0.6 μm to 0.8 μm to 1.0 μm, but it was 85 V or less regardless ofthe width.

On the other hand, when the trench DTR had an air-gap space SP, thebreakdown voltage BV remained virtually unchanged even though the widthW of the trench DTR was changed (0.6 μm, 0.8 μm, 1.0 μm), but it wasbetween 95 V and 100 V. This demonstrates that the breakdown voltage BVis higher when the trench DTR has an air-gap space SP than when it hasno air-gap space SR.

Furthermore, a test on field intensity distributions at breakdown in thesamples was conducted by isolation breakdown voltage simulations forcomparison between a DTI structure with an air-gap space in a trench DTRand one without an air-gap space therein. FIGS. 16A and 16B and FIGS.17A and 17B show the result of the test.

Referring to FIGS. 16A and 16B, in the case that the DTI structure hadno air-gap space SP in the trench DTR, it was found that the fieldintensity was the highest in the vicinity of the interface between then⁺ buried region NB and p⁻ epitaxial region EP1 which are in contactwith the trench DTR. At this time the breakdown voltage BV was 93 V.

Referring to FIGS. 17A and 17B, in the case that the DTI structure hadan air-gap space SP in the trench DTR, it was found that the fieldintensity was lower in the vicinity of the interface between the n⁺buried region NB and p⁻ epitaxial region EP1 which were in contact withthe trench DTR, than in the case shown in FIGS. 16A and 16B. At thistime the breakdown voltage BV was 126 V and higher than in the caseshown in FIGS. 16A and 16B.

These findings reveal that the filed intensity in an area in contactwith the trench DTR is lower and the breakdown voltage is higher whenthe trench DTR has an air-gap space SP than when it has no air-gap spaceSP.

Next, the advantageous effects of this embodiment will be described.According to this embodiment, since the trench DTR of the DTI structureis formed after completion of a device such as a high breakdown voltagelateral MOS transistor as shown in FIGS. 4 to 7, the trench DTR can befilled with the interlayer insulating film II. This makes it unnecessaryto form an insulating film to fill the trench DTR in addition to theinterlayer insulating film, leading to a substantial reduction in thenumber of manufacturing steps.

When the trench DTR of the DTI structure is formed after completion of adevice such as a high breakdown voltage lateral MOS transistor, there isanother advantageous effect. The surface of the insulating film to befilled in the trench DTR is less frequently subjected to wet etching inthe manufacturing steps after completion of the device than in themanufacturing steps before completion of the device. For this reason,even when there is an air-gap space SP inside the trench DTR, the spaceSP is less likely to be exposed on the substrate surface. Consequentlyit is unlikely that foreign substance such as photo-resist may get intothe space SP exposed on the substrate surface, which prevents a patterndefect due to spout of foreign substance front the air-gap space SPduring the manufacturing process.

Furthermore, since the air-gap space SP in the trench DTR is unlikely tobe exposed on the surface, there is no problem with the existence of theair-gap space SP in the trench DTR. Therefore, the trench DTR need nothave a high fillability, so the number of manufacturing steps can bedecreased.

In addition, by making an air-gap space SP in the trench DTR purposely,leak currents of the devices isolated by DTI structures are reduced,breakdown voltages are increased and the field intensity in an area incontact with the trench DTR is lowered, as explained referring to FIGS.13 to 17B.

Furthermore, by making an air-gap space SP in the trench DTR, theinfluence of an electric field from an adjacent device which hampersexpansion of a depletion layer (reverse field plate effect) issuppressed and as a consequence the isolation breakdown voltage isincreased. Also, by making an air-gap space SP in the trench DTR, stressin the trench DTR is reduced and crystal defects attributable to suchstress are thus suppressed.

Furthermore, since a DTI structure is formed in a region where an STIstructure exists, stress concentration on the opening of the trench DTRis relieved. This further suppresses crystal defects.

Second Embodiment

Although the first embodiment concerns a DTI structure which is formedin a region where an STI structure exists, a DTI structure may be formedin a region where no STI structure exists. The second embodiment, inwhich a DTI structure is formed in a region where no STI structureexists, is described below.

Referring to FIG. 18, an insulating film IL1, an insulating film IL2 anda mask film MK are stacked over the surface of a semiconductor substrateSUB in order. This process corresponds to the steps before photo-resistPRE coating in the first embodiment as shown in FIG. 5.

Referring to FIG. 19, anisotropic etching is performed on the mask filmMK, insulting film IL2 and insulating film IL1 in order by an ordinaryphotoengraving technique and an etching technique.

Then, anisotropic etching is performed on the semiconductor substrateSUB using the patterned mask film MK as a mask. Consequently, a trenchDTR extending inward from the surface of the semiconductor substrate SUBis made. After that, the mask film MK is removed by isotropic etching.

Referring to FIG. 20, as a result of the above isotropic etchingprocess, the upper surface of the insulating film IL2 is exposed.Insulating film 11A is formed over each device (not shown) and in thetrench DTR in a manner to cover the device and form an air-gap space SPin the trench DTR. For example, this insulating film 11A is made ofBP-TEOS.

After that, the same steps as those shown in FIGS. 10 to 12 in the firstembodiment are carried out to manufacture a semiconductor deviceaccording to the second embodiment in which a DTI structure is formed ina region where no STI structure exists.

According to the second embodiment, the DTI structure can be applied toa simple device without an STI structure.

Third Embodiment

Although the mask film MK is removed by isotropic etching in themanufacturing process according to the second embodiment, the mask filmMK need not necessarily be removed. The third embodiment, in which themask film MK is not removed, is described below.

The manufacturing method according to the third embodiment includes thesame steps as shown in FIGS. 18 and 19 in the second embodiment.Referring to FIG. 21, after these steps, insulating film 11A is formedover the mask film MK and in the trench DTR in a manner to cover thedevice (not shown) and form an air-gap space SP in the trench DTRwithout removing the mask film MK.

Then, the same steps as those shown in FIGS. 10 to 12 in the firstembodiment are carried out to manufacture a semiconductor device withthe mask film MK not removed according to the third embodiment.

According to the third embodiment, the step of removing the mask film MKis omitted, leading to further cost reduction and shorter turnaroundtime.

Fourth Embodiment

Although the insulating film IL1, insulating film IL2 and mask film MKare stacked in the manufacturing process according to the secondembodiment, the insulating film IL1 can be omitted. The fourthembodiment, in which the insulating film IL1 is omitted, is describedbelow.

Referring to FIG. 22, an insulating film IL2 and a mask film MK arestacked over the surface of a semiconductor substrate SUB in order. Thisprocess corresponds to the steps before photo-resist PRE coating asshown in FIG. 5 in the first embodiment.

Referring to FIG. 23, anisotropic etching is performed on the mask filmMK and insulating film IL2 using an ordinary photoengraving techniqueand an etching technique.

Then, anisotropic etching is performed on the semiconductor substrateSUB using the mask film MK as a mask. Consequently, a trench DTRextending inward from the surface of the semiconductor substrate SUB isformed. After that, the mask film MK is removed by isotropic etching.

Referring to FIG. 24, as a result of the isotropic etching process, theupper surface of the insulating film IL2 is exposed. Insulating film IIAis formed over each device and in the trench DTR in a manner to coverthe device and form an air-gap space SP in the trench DTR.

After that, the same steps as those shown in FIGS. 10 to 12 in the firstembodiment are carried out to manufacture a semiconductor deviceaccording to the fourth embodiment in which the insulating film IL1 isomitted.

According to the fourth embodiment, since the insulating film IL1 isomitted, further cost reduction and shorter turnaround time can beachieved.

Fifth Embodiment

Although the insulating film IL1, insulating film IL2 and mask film MKare stacked in the manufacturing process according to the thirdembodiment, the insulating film IL1 and insulating film IL2 can beomitted. The fifth embodiment, in which the insulating film IL1 andinsulating film IL2 are omitted, is described below.

Referring to FIG. 25, a mask film MK is formed in a manner to contactthe surface of a semiconductor substrate SUB directly. This stepcorresponds to the step before photoresist PRE coating as shown in FIG.5 in the first embodiment.

Referring to FIG. 26, anisotropic etching is performed on the mask filmMK using an ordinary photoengraving technique and an etching technique.

Then, anisotropic etching is performed on the semiconductor substrateSUB using the mask film MK as a mask. Consequently, a trench DTRextending inward from the surface of the semiconductor substrate SUB isformed.

Referring to FIG. 27, while the mask film MK is left or not removed,insulating film 11A is formed over the mask MK and in the trench DTR ina manner to cover each device and form an air-gap space SP in the trenchDTR.

After that, the same steps as those shown in FIGS. 10 to 12 in the firstembodiment are carried out to manufacture a semiconductor deviceaccording to the fifth embodiment in which the insulating film IL1 andinsulating film IL2 are omitted.

According to the fifth embodiment, since the insulating film IL1 andinsulating film IL2 are omitted, further cost reduction and shorterturnaround time can be achieved.

Sixth Embodiment

As shown in FIG. 28, device formation regions DFR (pMOS transistorformation regions in the case shown in the figure), each surrounded by aDTI structure, may be adjacent to each other with a specific region (SR)between them. In this case, an STI structure may be formed on thesurface of the semiconductor substrate SUB in the specific region SR. Asdescribed earlier, the STI structure includes a trench STR formed in thesurface of the semiconductor substrate SUB and an insulating film BILburied in the trench STR.

As shown in FIGS. 29 and 30, it is also possible that device formationregions DFR, each surrounded by a DTI structure, are adjacent to eachother with only one trench DTR between them.

When only one trench lies between device formation regions DFR, it ispreferable that devices formed in neighboring device formation regionsbe of the same type. In other words, if a pMOS transistor is formed in adevice formation region, it is preferable that a pMOS transistor beformed in a device formation region adjacent to that region.

If devices of the same type are formed in neighboring device formationregions DFR as mentioned above, the same well regions (n-type wellregion in the case of a pMOS transistor) are located on both sides ofthe trench DTR lying between the device formation regions, eliminatingthe possibility of a problem related to well region diffusion beforeformation of the trench DTR.

In the above explanations of the first to sixth embodiments, it has beenassumed that the device to be formed in a device formation region DFR isa high breakdown voltage MOS transistor. However, the present inventionmay also be applied to IGBTs (insulated gate bipolar transistors) anddiodes and other types of high breakdown voltage devices.

“Completion of a device” in the manufacturing process means that maincomponents which are required for the device to perform its functionhave been formed. More specifically, if the device is a diode,completion of the device means that an anode region and a cathode regionhave been formed; if the device is an MIS (metal insulationsemiconductor) transistor, it means that a source region, a drainregion, a gate insulating film, and a gate electrode have been formed;and if the device is an IGBT, it means that an emitter region, a baseregion, a drift region, a collector region, a gate insulating film and agate electrode have been formed.

In the explanations of the first to sixth embodiments, it has beenassumed that the interlayer insulating film II is, for example, alaminate comprised of BP-TEOS and a silicon oxide film formed by plasmaCVD. However, the interlayer insulating film II is not limited theretobut it may be made of different materials or be a single-layer film. Theinterlayer insulating film formed in the trench DTR is intended forelectric isolation between a device in a lower layer and a conductivelayer in an upper layer such as an interconnect, and includes a filmwhose upper surface is flattened.

In all the foregoing embodiments, if it is necessary to prevent solidphase diffusion of B (boron) or P (phosphor) in the interlayerinsulating film II, an insulating film (liner film), such as a siliconoxide film or silicon nitride film, may be formed on the inner wall ofthe trench DTR by oxidization or nitridation or CVD before deposition ofthe interlayer insulating film II.

It should be considered that the embodiments disclosed herein are allillustrative and not restrictive. It should be understood that the scopeof the invention is defined by the appended claims rather than by theabove description, and all changes that fall within metes and bounds ofthe claims, or equivalence of such metes and bounds, are intended to beembraced by the claims.

The present invention is particularly effective when it is applied tothe manufacture of a semiconductor device having a trench.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate having a trench in a main surface thereof; adevice being formed over the main surface of the semiconductorsubstrate; and an insulating film being formed over the device and inthe trench so as to cover the device and form an air-gap space in thetrench, wherein a side surface of the trench on a same level of a bottomof the air-gap space directly contacts the semiconductor substrate.
 2. Asemiconductor device according to claim 1 wherein, the device has aconductive portion, and the insulating film has a hole which reaches theconductive portion.
 3. A semiconductor device according to claim 1,wherein the trench is formed so as to surround the device when seen in aplan view.
 4. A method of manufacturing a semiconductor deviceincluding 1) a first semiconductor layer having a first conductivitytype, 2) a second semiconductor layer formed on the first semiconductorlayer and having a second conductivity type different from the firstconductivity type, 3) a third semiconductor layer formed on the secondsemiconductor layer and having the first conductivity type, and 4) a MOStransistor having a gate electrode over the third semiconductor layer,and source and drain regions in the third semiconductor layer, themethod comprising the steps of: (a) forming a first trench extendingfrom the third semiconductor layer to reach inside the firstsemiconductor layer, and surrounding the MOS transistor in plan view;(b) forming a first insulating film covering the gate electrode andfilling the first trench, while leaving an air-gap in the first trench;and (c), before the step (a), forming a second trench in the thirdsemiconductor layer, wherein the first trench penetrates through thesecond semiconductor layer, wherein the first trench is formed in thesecond trench, and wherein the air-gap extends from the thirdsemiconductor layer through the second semiconductor layer to the firstsemiconductor layer.
 5. The method of manufacturing a semiconductordevice according to claim 4, wherein a bottom of the air-gap is locatedin the first semiconductor layer.
 6. The method of manufacturing asemiconductor device according to claim 4, wherein the second trench isfilled with a second insulating film, and wherein an isolation regionincluding the second trench contacts the source or drain region in thethird semiconductor layer.
 7. The method of manufacturing asemiconductor device according to claim 6, wherein the first trenchsurrounds the MOS transistor and the isolation region in plan view. 8.The method of manufacturing a semiconductor device according to claim 6,wherein the step (a) further includes: (a-1) forming a mask film overthe MOS transistor and the third semiconductor layer; and (a-2)performing anisotropic etching to form the first trench in the first tothird semiconductor layers by using the mask film.
 9. The method ofmanufacturing a semiconductor device according to claim 8, wherein themask film comprises silicon oxide (SiO).
 10. The method of manufacturinga semiconductor device according claim 4, after the step (b), furthercomprising the steps of: (d) forming a conductive layer in the firstinsulating film to reach the source or drain region; and (e) forming aninterconnecting layer, on the first insulating film, connected to theconductive layer.
 11. The semiconductor device according to claim 4,wherein the first semiconductor layer includes a semiconductor substrateand an epitaxial region formed on the semiconductor substrate.